Sigma-delta modulators are analog-to-digital converters arranged to receive an analog input signal and output a digital signal in which the relative density of ‘ones’ and ‘zeros’ is proportional to the voltage level of the analog input signal.
A simple sigma-delta modulator is shown in FIG. 1. The sigma-delta modulator receives an analog input signal 101 which is input into a summation unit 102. The summation unit sums the analog input signal with a feedback signal output by a digital-to-analog converter (DAC) 106 in the feedback path. The summed signal is then integrated by integrator 103 and passed to a quantizer 104 that compares the integrated signal with one or more threshold voltages and outputs a digital output signal 105 in dependence on that comparison. The digital-to-analog converter receives the digital output signal and converts it into an analog signal for summing with the analog input signal.
The purpose of the feedback signal is to maintain the average output of the integrator near the comparator's reference level by making the ones and zeros of the digital output signal representative of the analog input signal.
The input range of the sigma-delta modulator is set by the upper and lower voltage limits of the analog feedback signal. The relative proportions of ‘ones’ and ‘zeros’ in the digital output signal represent the voltage level of the analog input signal relative to the input range of the modulator. If, for example, the input range of the modulator is 0 to 5V and the voltage level of the input signal is 2.5V, the digital output signal should contain 50% ‘ones’ and 50% ‘zeros’. If the input signal exceeds the input range of the modulator then the digital output signal does not correctly represent the voltage level of the input signal.
The quantizer is preferably arranged to sample the integrated signal at high frequency. A high sampling frequency provides noise performance benefits. Oversampling causes quantization noise to be spread over a wider frequency range but oversampling does not change the signal-to-noise ratio. Therefore, oversampling has the effect of decreasing noise magnitude over the frequency range of interest. The sigma-delta modulator may suitably be followed by a low-pass filter to remove the high frequency noise.
Oversampling alone does not account for the high resolution offered by sigma-delta modulators. The sampling frequency that would be required to achieve high resolution modulation is typically too high to be practicably realizable. Instead, further noise performance benefits are provided by the integrator, which ‘shapes’ noise out of low frequencies and into higher frequencies. This further reduces the noise magnitude over the frequency range of interest. Once again, the noise ‘shaped’ into higher frequencies can be removed by filtering the digital output signal.
The sigma-delta modulator shown in FIG. 1 is a simple, first-order sigma-delta modulator. Further complexity can be introduced by having a multi-bit quantizer rather than a single bit quantizer and by having more than one integrator.
Sigma-delta modulators are commonly implemented as discrete-time systems in which voltage levels are propagated through the modulator at each clock period. However, continuous-time implementations also exist and typically offer power-saving advantages over discrete-time implementations, together with higher input bandwidths.
An example of a continuous-time sigma-delta modulator is shown in FIG. 2. The analog input signal 201 is combined with a feedback signal, which in this example is provided by current source 206, before being passed to an integrator 207. In this example the integrator comprises an operational amplifier 202 and a capacitor 203. The integrated signal is received by the quantizer 204 to form a digital output signal 205. The digital output signal is fed back via the feedback loop and input into the current source to generate a suitable feedback signal for combining with the analog input signal.
The current source in FIG. 2 effectively injects pulses of current into the summing junction at each clock transition. The aim is to maintain zero average current into the summing junction. However, the total charge injected into the summing injection during a clock pulse is dependent on the length of that pulse. Theoretically, the time between each clock transition should be of identical duration. However, in reality clock jitter means that the time between clock transitions can vary slightly with time. This causes noise that directly modulates the feedback signal and adds directly to the analog input signal. This additional noise can cause significant degradation in the performance of a sigma-delta modulator.
A further source of noise in a sigma-delta modulator is quantizer metastability. When the input signal to a quantizer is near a threshold level, the quantizer takes more time than usual to stabilise at one output level. This results in a feedback current that is not well defined, which is equivalent to injecting a large error into the summing junction. This phenomenon causes ‘noise filling’ in which high frequency quantization noise is ‘folded’ into the frequency band of interest. This problem limits the performance of the modulator and increases with modulator order.
Additional performance limitations result from the non-linearity and non-ideal transfer function of the integrator. Non-linearity of the integrator causes quantization noise to be ‘folded’ into the frequency band of interest. A non-ideal transfer function of the integrator at high frequencies modifies the noise shaping function of the modulator. It also introduces an extra delay into the loop. For high frequency and high bandwidth continuous time implementations this can be one of the main issues affecting the stability of the modulator.
Because of the performance limitations described above, many existing implementations of continuous-time sigma-delta modulators use switched capacitors and multi-bit quantizers. An example of such a sigma-delta modulator is shown in FIG. 3. This sigma-delta modulator includes a switched capacitor 306 for receiving the input signal 301. The modulator includes an integrator 302 and a current source 305 as before. The modulator also incorporates a multi-bit quantizer 303. The multi-bit quantizer causes jitter sensitivity to be reduced by 2N, where N is the number of bits output by the quantizer at any given time instant and received by the DAC in the feedback path.
Although incorporating a switched capacitor and/or a multi-bit quantizer into a sigma-delta modulator helps to address the problems caused by clock jitter, both the switched capacitor and the multi-bit quantizer introduce additional problems of their own. First, the switched capacitor limits the maximum signal bandwidth. Second, the switched capacitor introduces a delay into the modulator that effectively returns the modulator to a discrete time implementation. Finally, the operational amplifier of the integrator has to ‘swallow’ the charge introduced by the switched capacitor in one sampling period, which requires the operational amplifier to settle quickly. The gain-bandwidth product of the operational amplifier then needs to be equivalent to that of the switched capacitor, which cancels the power saving potential of a continuous-time implementation. Using a multi-bit quantizer can cause DAC non-linearity, which causes noise folding, and increased quantizer power consumption.
There is therefore a need for an improved sigma-delta modulator that addresses the problems outlined above.